
`include "defines.v"

//----------------------------------------------------------------
//Module Name : MEMWB_reg.v
//Description of module:
//
//----------------------------------------------------------------
//Designer:	Tang Pengyu
//Date: 2021/9/28/15:16  
//----------------------------------------------------------------
module	MEMWB_reg(
	input	clk,
	input	memwb_rst,
	input	memwb_ena,
//from if
	input	[`INST_ADDR_LEN-1:0]	i_ifififif_pc_out,
	input	i_ifififif_fetched,
//	input	i_ifififif_time_intr_r,
	input	[`INST_ADDR_LEN-1:0]	i_ifififif_addr,
	
//from id
	input	i_ididid_rs1_r_ena,				//--csr_reg,regfile
	input	[4:0]	i_ididid_rs1_r_addr,	//--csr_reg,regfile
	input	i_ididid_rs2_r_ena,				//--regfile
	input	[4:0]	i_ididid_rs2_r_addr,	//--regfile
	input	i_ididid_rd_w_ena,				//--csr_reg,regfile
	input	[4:0]	i_ididid_rd_w_addr,		//--csr_reg,regfile
	input	[`REG_DATA_LEN-1:0] i_ididid_op2,	//rge
//from ctrlid
	input	[1:0]	i_ctrlidctrlidctrlid_wb_sel,			//regfile
	input	i_ctrlidctrlidctrlid_ecall_en,					//wb
	input	i_ctrlidctrlidctrlid_mret_en,					//wb
//from exe
	input	[`REG_DATA_LEN-1:0]	i_exeexe_data,		//--WB
//from CSR_UNIT
	input	[11:0]	i_csrunitcsrunit_csr_addr,		//wb
	input	i_csrunitcsrunit_csr_w_ena,			//wb
	input	[`REG_DATA_LEN-1:0]	i_csrunitcsrunit_csr_w_data,		//wb
	input	i_csrunitcsrunit_csr_r_ena,			//wb
	input	[63:0]	i_csrunitcsrunit_csr_r_data,
//from ctrlexe
	input	i_ctrlexectrlexe_load_axi_en,			//regfile
	input	i_ctrlexectrlexe_load_clint_en,		//regfile
	input	i_ctrlexectrlexe_store_clint_en,

//from	ls_pro
	input	[63:0]	i_lspro_axi_ld_data,
	input	i_lspro_fetched,
	
//from clint
	input	[63:0]	i_clintclint_load_data,

	output	reg [`INST_ADDR_LEN-1:0]	o_ifififif_pc_out,
	output	reg o_ifififif_fetched,
//	output	reg o_ifififif_time_intr_r,
	output	reg	[`INST_ADDR_LEN-1:0]	o_ifififif_addr,

	output	reg o_ididid_rs1_r_ena,				//--csr_reg,regfile
	output	reg [4:0]	o_ididid_rs1_r_addr,	//--csr_reg,regfile
	output	reg o_ididid_rs2_r_ena,				//--regfile
	output	reg [4:0]	o_ididid_rs2_r_addr,	//--regfile
	output	reg o_ididid_rd_w_ena,				//--csr_reg,regfile
	output	reg [4:0]	o_ididid_rd_w_addr,		//--csr_reg,regfile
	output	reg [`REG_DATA_LEN-1:0] o_ididid_op2,	
	
	output	reg [1:0]	o_ctrlidctrlidctrlid_wb_sel,			//regfile
	output	reg o_ctrlidctrlidctrlid_ecall_en,					//wb
	output	reg o_ctrlidctrlidctrlid_mret_en,					//wb
	
	output	reg [`REG_DATA_LEN-1:0]	o_exeexe_data,		//--WB
	
	output	reg [11:0]	o_csrunitcsrunit_csr_addr,		//wb
	output	reg o_csrunitcsrunit_csr_w_ena,			//wb
	output	reg [`REG_DATA_LEN-1:0]	o_csrunitcsrunit_csr_w_data,		//wb
	output	reg o_csrunitcsrunit_csr_r_ena,			//wb
	output	reg [63:0]	o_csrunitcsrunit_csr_r_data,
	
	output	reg o_ctrlexectrlexe_load_axi_en,			//regfile
	output	reg o_ctrlexectrlexe_load_clint_en,		//regfile
	output	reg o_ctrlexectrlexe_store_clint_en,
	
	output	reg [63:0]	o_lspro_axi_ld_data,
	output	reg o_lspro_fetched,
	
	output	reg [63:0]	o_clintclint_load_data

);
always @(posedge clk)	begin
	if(memwb_rst)	begin
		o_ifififif_pc_out <= {`INST_ADDR_LEN{1'b0}};
		o_ifififif_fetched <= 1'b0;
//		o_ifififif_time_intr_r <= 1'b0;
		o_ifififif_addr <= {`INST_ADDR_LEN{1'b0}};
		
		o_ididid_rs1_r_ena <= 1'b0;
		o_ididid_rs1_r_addr <= 5'd0;
		o_ididid_rs2_r_ena <= 1'b0;
		o_ididid_rs2_r_addr <= 5'd0;
		o_ididid_rd_w_ena <= 1'b0;
		o_ididid_rd_w_addr <= 5'd0;
		o_ididid_op2 <= {`REG_DATA_LEN{1'b0}};
		
		o_ctrlidctrlidctrlid_wb_sel <= 2'b00;
		o_ctrlidctrlidctrlid_ecall_en <= 1'b0;
		o_ctrlidctrlidctrlid_mret_en <= 1'b0;
		
		o_exeexe_data <= {`REG_DATA_LEN{1'b0}};
		
		o_csrunitcsrunit_csr_addr <= 12'd0;
		o_csrunitcsrunit_csr_w_ena <= 1'b0;
		o_csrunitcsrunit_csr_w_data <= {`REG_DATA_LEN{1'b0}};
		o_csrunitcsrunit_csr_r_ena <= 1'b0;
		o_csrunitcsrunit_csr_r_data <= 64'd0;
		
		o_ctrlexectrlexe_load_axi_en <= 1'b0;
		o_ctrlexectrlexe_load_clint_en <= 1'b0;
		o_ctrlexectrlexe_store_clint_en <= 1'b0;
		
		o_lspro_axi_ld_data <= 64'd0;
		o_lspro_fetched <= 1'b0;
		
		o_clintclint_load_data <= 64'd0;
	
	end
	else if(memwb_ena)	begin
		o_ifififif_pc_out <= i_ifififif_pc_out;
		o_ifififif_fetched <= i_ifififif_fetched;
//		o_ifififif_time_intr_r <= i_ifififif_time_intr_r;
		o_ifififif_addr <= i_ifififif_addr;
		
		o_ididid_rs1_r_ena <= i_ididid_rs1_r_ena;
		o_ididid_rs1_r_addr <= i_ididid_rs1_r_addr;
		o_ididid_rs2_r_ena <= i_ididid_rs2_r_ena;
		o_ididid_rs2_r_addr <= i_ididid_rs2_r_addr;
		o_ididid_rd_w_ena <= i_ididid_rd_w_ena;
		o_ididid_rd_w_addr <= i_ididid_rd_w_addr;
		o_ididid_op2 <= i_ididid_op2;
		
		o_ctrlidctrlidctrlid_wb_sel <= i_ctrlidctrlidctrlid_wb_sel;
		o_ctrlidctrlidctrlid_ecall_en <= i_ctrlidctrlidctrlid_ecall_en;
		o_ctrlidctrlidctrlid_mret_en <= i_ctrlidctrlidctrlid_mret_en;
		
		o_exeexe_data <= i_exeexe_data;
		
		o_csrunitcsrunit_csr_addr <= i_csrunitcsrunit_csr_addr;
		o_csrunitcsrunit_csr_w_ena <= i_csrunitcsrunit_csr_w_ena;
		o_csrunitcsrunit_csr_w_data <= i_csrunitcsrunit_csr_w_data;
		o_csrunitcsrunit_csr_r_ena <= i_csrunitcsrunit_csr_r_ena;
		o_csrunitcsrunit_csr_r_data <= i_csrunitcsrunit_csr_r_data;
		
		o_ctrlexectrlexe_load_axi_en <= i_ctrlexectrlexe_load_axi_en;
		o_ctrlexectrlexe_load_clint_en <= i_ctrlexectrlexe_load_clint_en;
		o_ctrlexectrlexe_store_clint_en <= i_ctrlexectrlexe_store_clint_en;
		
		o_lspro_axi_ld_data <= i_lspro_axi_ld_data;
		o_lspro_fetched <= i_lspro_fetched;
		
		o_clintclint_load_data <= i_clintclint_load_data;

	end
end

endmodule